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Preliminary FIN12AC PSerDes
April 2005 Revised May 2005
FIN12AC PSerDes Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
General Description
The FIN12AC is a 12-bit serializer capable of running a parallel frequency range between 5MHz and 56MHz. The frequency range is selected by the S1 and S2 control signals. The bi-directional data flow is controlled through use of a direction (DIRI) control pin. The devices can be configured to operate in a unidirectional mode only by hardwiring the DIRI pin. An internal PLL generates the required bit clock frequency for transfer across the serial link. Options exist for dual or single PLL operation dependent upon system operational parameters. The device has been designed for low power operation and utilizes Fairchild Proprietary Low Power CTL interface. The device also supports an ultra low power Power-Down mode for conserving power in battery operated applications.
Features
s Low power consumption s Fairchild Proprietary Low Power CTL interface s LVCMOS parallel I/O interface
* 2 mA source/sink current * Over-voltage tolerant control signals
s I/O power supply range between 1.65V and 3.6V s Analog Power Supply range of 2.775V r 5% s Multi-Mode operation allows for a single device to operate as Serializer or Deserializer s Internal PLL with no external components s Standby Power-Down mode support s Small footprint 32-terminal MLP packaging s Built in differential termination s Supports external CKREF frequencies between 5MHz and 56MHz s Serialized data rate up to 784Mb/s
Ordering Code:
Order Number FIN12ACGFX (Preliminary) FIN12ACMLX Package Number BGA42A MLP032A Package Description Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Pb-Free 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in Tape and Reel only.
PSerDes is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500915
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Preliminary FIN12AC Functional Block Diagram
Connection Diagram
Terminal Assignments for MLP
(Top View)
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Preliminary FIN12AC Pin Description
Pin Name DP[1:12] CKREF STROBE CKP DSO / DSI DSO / DSI I/O Type I/O IN IN OUT DIFF-I/O Number of Pins 12 1 1 1 2 Description of Signals LVCMOS Parallel I/O. Direction controlled by DIRI terminal. LVCMOS Clock Input and PLL Reference LVCMOS Strobe Signal for Latching Data into the Serializer LVCMOS Word Clock Output CTL Differential Serial I/O Data Signals (Note ) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I): Positive signal of DSO(I) pair DSO(I): Negative signal of DSO(I) pair CTL Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI: Positive signal of CKSI pair CKSI: Negative signal of CKSI pair CTL Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO: Positive signal of CKSO pair CKSO: Negative signal of CKSO pair LVCMOS Mode Selection terminals used to define frequency range for the RefClock, CKREF LVCMOS Control Input Used to control direction of Data Flow: DIRI "1" Serializer, DIRI "0" Deserializer LVCMOS Control Output Inversion of DIRI Power Supply for Parallel I/O and Translation Circuitry Power Supply for Core and Serial I/O Power Supply for Analog PPL Circuitry Use Bottom Ground Plane for Ground Signals
CKSI, SKSI
DIFF-IN
2
CKSO, CKSO DIFF-OUT
2
S1 S2 DIRI
IN IN IN
1 1 1
DIRO VDDP VDDS VDDA GND
OUT Supply Supply Supply Supply
1 1 1 1 0
Note 1: The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial connections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross.
Control Logic Circuitry
The FIN12AC has the ability to be used as a 12-bit Serializer or a 12-bit Deserializer. Terminals S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. The table below shows the terminal programming of these options based on the S1 and S2 control terminals. The DIRI terminal controls whether the device is the serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI terminal is asserted HIGH, the device will be configured as a serializer. Changing the state on the DIRI signal will reverse the direction of the I/O signals and generate the opposite state signal on DIRO. For unidirectional operation the DIRI terminal should be hardwired to the HIGH or LOW state and the DIRO terminal should be left floating. For bi-directional operation the DIRI of the master device will be driven by the system and the DIRO signal of the master will be used to drive the DIRI of the slave device. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to insure that no contention occurs between the deserializer outputs and the other 3
devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH Impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer the dedicated outputs will remain at the last logical value asserted. This value will only change if the device is once again turned around into a deserializer and the values are overwritten. TABLE 1. Control Logic Circuitry Mode S2 S1 DIRI Number 0 1 0 0 0 2 1 1 3 1 1 0 1 1 0 0 1 1 X 1 0 1 0 1 0 Description Power-Down Mode 12-Bit Serializer, 20MHz to 56MHz CKREF 12-Bit Deserializer 12-Bit Serializer, 5MHz to 15MHz CKREF 12-Bit Deserializer 12-Bit Serializer, 10MHz to 30MHz CKREF 12-Bit Deserializer
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Preliminary FIN12AC Power-Down Mode
Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state the PLL and references will be disabled, differential input buffers will be shut off, differential output buffers will be placed into a HIGH Impedance state, LVCMOS outputs will be placed into a HIGH Impedance state, and LVCMOS inputs will be driven to a valid level internally. Additionally all internal circuitry will be reset. The loss of CKREF state is also enabled to insure that the PLL will only power-up if there is a valid CKREF signal. In a typical application mode signals of the device will not change other than between the desired frequency range and the power-down mode. This allows for system level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a "logic 0" should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a "logic 1" should be connected to a system level power-down signal. ing edge of the STROBE signal and then serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When operating in this mode the internal deserializer circuitry is disabled including the DS input buffer. The CKSI serial inputs remain active to allow the pass through of the CKSI signal to the CKP output. For more on this mode please see the section on Passing a Word Clock. If this mode is not needed then the CKSI inputs can either be driven to valid levels or left to float. For lowest power operation let the CKSI inputs float. Serializer Operation: (Figure ) DIRI equals 1 CKREF does not equal STOBE If the same signal is not used for CKREF and STROBE, then the CKREF signal must be run at a higher frequency than the STROBE rate in order to serialize the data correctly. The actual serial transfer rate will remain at 14 times the CKREF frequency. A data value of zero will be sent when no valid data is present in the serial bit stream. The operation of the serializer will otherwise remain the same. The exact frequency that the reference clock needs to run at will be dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology then the minimum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-cycle variation then the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. Serializer Operation: (Figure ) DIRI equals 1 No CKREF A third method of serialization can be done by providing a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up the device is configured to accept a serialization clock from CKSI. If a CKREF is received then this device will enable the CKREF serialization mode. The device will remain in this mode even if CKREF is stopped. To re-enable this mode the device must be powered down and then powered back up with "logic 0" on CKREF.
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially identical in these modes but the actual data and clock streams will differ dependent on if CKREF is the same as the STROBE signal or not. When it is stated that CKREF STROBE this means that the CKREF and STROBE signals have an identical frequency of operation but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE then each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. Serializer Operation: (Figure ) Modes 1, 2, or 3 DIRI equals 1 CKREF equals STROBE The PLL must receive a stable CKREF signal in order to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked the device can begin to capture and serialize data. Data will be captured on the ris-
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Preliminary FIN12AC Serializer Operation Mode
(Continued)
FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)
FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)
FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
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Preliminary FIN12AC Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this mode the internal serializer circuitry is disabled including the parallel data input buffers. If there is a CKREF signal provided then the CKSO serial clock will continue to transmit bit clocks. Deserializer Operation: DIRI equals 0 (Serializer Source: CKREF equals STROBE) When the DIRI signal is asserted LOW the device will be configured as a deserializer. Data will be captured on the serial port and deserializer through use of the bit clock sent with the data. The word boundary is defined in the actual clock and data signal. Parallel data will be generated at the time the word boundary is detected. The falling edge of CKP will occur coincident with the data transition. The rising edge of CKP will be generated approximately 7 bit times later. When no embedded word boundary occurs then no pulse on CKP will be generated and CKP will remain HIGH. Deserializer Operation: PwrDwn equals 1 DIRI equals 0 (Serializer Source: CKREF does not equal STROBE) The logical operation of the deserializer remains the same regardless of if the CKREF is equal in frequency to the STROBE or at a higher frequency than the STROBE. The actual serial data stream presented to the deserializer will however be different because it will have non-valid data bits sent between words. The duty cycle of CKP will vary based on the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal will be equal to the STROBE frequency. The falling edge of CKP will coincident with data transition. The LOW time of the CKP signal will be equal to 1/2 (7 bit times) of the CKREF period. The CKP HIGH time will be equal to STROBE period 1/2 of the CKREF period. Figure is representative of a waveform that could be seen when CKREF is not equal to STROBE. If CKREF was significantly faster than additional non-valid data bits would occur between data words.
FIGURE 4. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
FIGURE 5. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
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Preliminary FIN12AC Embedded Word Clock Operation
The FIN12AC sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been implemented by skipping a low clock pulse. This appears in the serial clock stream as 3 consecutive bit times where signal CKSO remains HIGH. In order to implement this sort of scheme two extra data bits are required. During the word boundary phase the data will toggle either HIGH-then-LOW or LOW-then-HIGH dependent upon the last bit of the actual data word. Table provides some examples showing the actual data word and the data word with the word boundary bits added. Note that a 12-bit word will be extended to 14 bits during serial transmission. Bit 13 and Bit 14 are defined with-respect-to Bit 12. Bit 13 will always be the inversion of Bit 12 and Bit 14 will always be the same as Bit 12. This insures that a "0" o "1" and a "1" o "0" transition will always occur during the embedded word phase where CKSO is HIGH. The serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. The deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. The deserializer only uses the embedded word boundary information to find and capture the data. These boundary bits are then stripped prior to the word being sent out of the parallel port.
TABLE 2. Word Boundary Data Bits 12 Bit Data Words Hex FFFh 555h xxxh xxxh Binary 1111 1111 1111b 0101 01010 0101b 0xxx xxxx xxxxb 1xxx xxxx xxxxb 12 Bit Data Word with Word Boundary Hex 2FFFh 1555h 1xxxh 2xxxh Binary 10 1111 1111 1111b 01 0101 0101 0101b 01 0xxx xxxx xxxxb 10 1xxx xxxx xxxxb
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value equal to 1/2 of VDDP. The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source/sink current of 2 mAs at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH the bi-directional LVCMOS I/ Os will be in HIGH-Z state. Under purely capacitive load conditions the output will swing between GND and VDDP. The LVCMOS I/O buffers incorporate bushold functionality to allow for pins to maintain state when they are not driven. The bushold circuitry only consumes power during signal transitions.
Differential I/O Circuitry
. The FIN12AC employs FSC proprietary CTL I/O technology. CTL is a low power, low EMI differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses the current difference and direction from the corresponding output buffer to which it is connected. This differs from LVDS which uses a constant current source output but a voltage sense receiver. Like LVDS an input source termination resistor is required to properly terminate the transmission line. The FIN12AC device incorporates an internal termination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated termination resistor insures proper termination regardless of direction of data flow. The relative greater sensitivity of the current sense receiver of CTL allows it to work at much lower current drive and correspondingly a much lower voltage. During power-down mode the differential inputs will be disabled and powered down and the differential outputs will be placed in a HIGH-Z state. CTL inputs have an inherent failsafe capability that supports floating inputs. When the CKSI input pair of the serializer is unused it can reliably be left floating. Alternately both of the inputs can be connected to ground. CTL inputs should never be connected to VDD. When the CKSO output of the deserializer is unused it should be allowed to float.
FIGURE 6. LVCMOS I/O
FIGURE 7. Bi-directional Differential I/O Circuitry
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Preliminary FIN12AC PLL Circuitry
The CKREF input signal is used to provide a reference to the PLL. The PLL will generate internal timing signals capable of transferring data at 14 times the incoming CKREF signal. The output of the PLL is a Bit Clock that is used to serialize the data. The bit clock is also sent source synchronously with the serial data stream. There are two ways to disable the PLL. The PLL can be disabled by entering the Mode 0 state. (S1 S2 0). The PLL will disable immediately upon detecting a LOW on both the S1 and S2 signals. When any of the other modes are entered by asserting either S1 or S2 HIGH and by providing a CKREF signal the PLL will power-up and goes through a lock sequence. You must wait specified number of clock cycles prior to capturing valid data into the parallel port. An alternate way of powering down the PLL is by stopping the CKREF signal either HIGH or LOW. Internal circuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references will not however be disabled allowing for the PLL to power-up and re-lock in a lesser number of clock cycles than when exiting Mode 0. When a transition is seen on the CKREF signal the PLL will once again be reactivated.
Passing a Word Clock
For some applications it is desirable to pass a word clock through the deserializer to the serializer and output it as a reference clock for another device. (See Figure ) This can be done under the following conditions: 1. The application mode is unidirectional only. 2. The master word clock is generated on the same side of the cable as the deserializer. To implement pass through functionality on the deserializer: 1. DIRI LOW 2. CKREF LOW 3. Word clock should be connected to the STROBE. 4. This will pass the STROBE signal out the CKSO port. To implement pass through functionality on the serializer: 1. Connect CKSO of the deserializer to CKSI of the serializer 2. CKSI passes the signal to CKP 3. CKP must be connected to CKREF If the word clock being passed through the serializer stops then the serializer must be placed in the reset mode (MODE 0) and restarted before the CKSI signal will again pass through to CKP. If CKREF of the deserializer is running then a high speed bit clock will be passed across the flip instead of STROBE. This bit clock will be used as the clock source by the serializer provided that no CKREF signal exists on the serializer.
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Preliminary FIN12AC Application Mode Diagrams
Modes 1, 2, 3: Unidirectional Data Transfer
FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure shows the basic operation diagram when a pair of SerDes is configured in an unidirectional operation mode. Master Operation: The device will... (Please refer to Figure ) 1. During power-up the device will be configured as a serializer based on the value of the DIRI signal. 2. Accept CKREF_M word clock and generate a bit clock with embedded word boundary. This bit clock will be sent to the slave device through the CKSO port. 3. Receive parallel data on the rising edge of STROBE_M. 4. Generate and transmit serialized data on the DS signals which is source synchronous with CKSO. 5. Generate an embedded word clock for each strobe signal. Slave Operation: The device will... 1. Be configured as a deserializer at power-up based on the value of the DIRI signal. 2. Accept an embedded word boundary bit clock on CKSI. 3. Deserialize the DS Data stream using the CKSI input clock. 4. Write parallel data onto the DP_S port and generate the CKP_S. CKP_S will only be generated when a valid data word occurs.
FIGURE 9. Unidirectional Serializer and Deserializer
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Preliminary FIN12AC Application Mode Diagrams
(Continued)
FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction
FIGURE 11. 8-Bit Camera Interface (10MHz to 30MHz Parallel Operation) Figure shows an 8-bit LCD Interface with VSYNC/HSYNC capability. This interface is a very straightforward in implementing the PSerDes devices. Note that two additional data bits are still available for implementing additional data bits or control signals. Figure shows an application for a camera interface for a flip phone using the FIN12AC. For this application the reference clock is generated on the baseband side of the flip and passed across the SerDes pair differentially. This signal is then reconverted to a single ended signal for use as a reference clock by the imager. For some applications it may be possible to connect the REFCK directly to the CKREF signal of the FIN12AC serializer.
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Preliminary FIN12AC Absolute Maximum Ratings(Note )
Supply Voltage (VDD) ALL Input/Output Voltage CTL Output Short Circuit Duration Storage Temperature Range (TSTG) Maximum Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 4 seconds) ESD Rating Human Body Model, 1.5K:, 100pF Machine Model, 0:, 200pF
0.5V to 4.6V 0.5V to 4.6V
Continuous
Recommended Operating Conditions
Supply Voltage (VDDA, VDDS) Supply Voltage (VDDP) Operating Temperature (TA) (Note ) Supply Noise Voltage (VDDA-PP) 2.775V r 5.0%V 1.65V to 3.6V
65qC to 150qC 150qC 260qC !2kV !200V
10qC to 70qC
100 mVP-P
Note 2: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol LVCMOS I/O VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage IOH VOL Output Low Voltage IOL IIN IOFF Input Current Input/Output Power-Off Leakage Current DIFFERENTIAL I/O (Note ) IODH IODL IOS IOZ ITH ITL IIZ IIS VICM RTRM Output HIGH Source Current Output LOW Sink Current Short Circuit Output Current Disabled Output Leakage Current Differential Input Threshold LOW Current Disabled Input Leakage Current Short Circuit Input Current Input Common Mode Range CKSI, DS Internal Receiver Termination Resistor VOS VOS VOUT 1.0V Figure 1.0V Figure 0V Driver Enabled Driver Disabled CKSO, DSO 0V to VDDS, S2 S1 0V 50.0 TBD TBD VIN VDDP 2.0 mA 0V to 3.6V 0V, VDDP 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 0.25 x VDDP V 0.75 x VDDP V 0.65 x VDDP GND VDDP 0.35 x VDDP V Parameter Test Conditions Min Typ (Note ) Max Unit
2.0 mA
VDDP VDDP VDDP VDDP VDDP
5.0
5.0
PA PA
ALL LVCMOS Inputs/ Outputs 0V to 3.6V
r5.0
PA PA
mA
r5.0 r1.0 r5.0 50.0
PA PA PA PA PA
mA V
Differential Input Threshold HIGH Current See Figure and Table See Figure and Table CKSI, DSI VOUT VDDS VID 0V to VDDS, S2 S1 0V
r1.0
0.5 100
r5.0
VDDS-1
VDDS 2.775 r 5% 50mV, VIC 925mV, DIR I 0 VID
|CKSI - CKSI |
:
Note 3: Typical Values are given for VDD 2.5V and TA 25qC. Positive current values refer tot the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to Ground unless otherwise specified (except 'VOD and VOD). Note 4: Typical values are given for VDDP 2.75V and T A 25qC.
Note 5: The definition of short-circuit includes all the possible situations. For example, the short of differential pairs to Ground, the short of differential pairs (No Grounding) and either line of differential pairs tied to Ground.
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Preliminary FIN12AC Power Supply Currents
Symbol IDDA1 IDDA2 IDDS1 IDDS2 IDDS IDD_PD IDD_SER1 Parameter VDDA Serializer Static Supply Current VDDA Deserializer Static Supply Current VDDS Serializer Static Supply Current VDDS Deserializer Static Supply Current VDDA Static Supply Current VDD Power-Down Supply Current IDD_PD IDDA IDDS IDDP 14:1 Dynamic Serializer Power Supply Current (Note ) IDD_SER1 IDDA IDDS IDDP CKREF DIRI H STROBE Test Conditions All DP and Control Inputs at 0V or VDD NOCKREF, S2 NOCKREF, S2 NOCKREF, S2 NOCKREF, S2 S1 S1 S2 S2 0 0, S2 S1 S2 S1 S2 S1 IDD_DES1 14:1 Dynamic Deserializer Power Supply Current (Note ) IDD_DES1 IDDA IDDS IDDP CKREF DIRI L STROBE S2 S1 S2 S1 S2 S1 IDD_SER2 14:1 Dynamic Serializer Power Supply Current (Note ) IDD_SER2 IDDA IDDS IDDP NOCKREF STROBEo Active CKSI DIRI 8X STROBE H H 5 MHz L 15 MHz H 10 MHz H 30 MHz L 30 MHz H 56 MHz H 5 MHz L 15 MHz H 10 MHz H 30 MHz L 30 MHz H 56 MHz 5 MHz 15 MHz 10 MHz 30 MHz 56 MHz TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0, S1 0, S1 0, S1 0, S1 1, DIR 1, DIR 1, DIR 1, DIR 1 0 1 0 All DP and Control Inputs at 0V or VDD All DP and Control Inputs at 0V or VDD All DP and Control Inputs at 0V or VDD All DP and Control Inputs at 0V or VDD Min Typ TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD 5.0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA Units mA mA mA mA mA uA
All Inputs at GND or VDD
See Figure
See Figure
See Figure
Note 6: The worst case test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference frequency unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD 2.5V.
AC Specification: Serializer Timing Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol tTCP Parameter CKREF Clock Period (5 MHz - 56MHz) fREF CKREF Frequency Relative to Strobe Frequency tTCH tTCL tCLKT tTCH tTCL fMAX CKREF Clock High Time CKREF Clock Low Time LVCMOS Input Transition Time STROBE Pulse Width HIGH STROBE Pulse Width LOW Maximum Serial Data Rate REFCK x 14 Figure Figure Figure S2 S2 S2 0 1 1 S1 S1 S1 1 0 1 5.0 5.0 70.0 140 420 210 420 784 Mb/s Test Conditions See Figure CKREF CKREF Does Not Equal STROBE STROBE S2 S2 S2 S2 S2 S2 1 1 0 1 1 0 S1 S1 S1 S1 S1 S1 0 1 1 0 1 1 TBD TBD 0.5 0.5 1.1 *fST Min 66.0 33.0 17.8 T Typ Max 166 100 33.0 15.0 30.0 56.0 TBD TBD TBD T T ns ns ns MHz ns Units
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Preliminary FIN12AC Serializer AC Electrical Characteristics
Serializer Timing Characteristics
Symbol tTLH tTHL tSTC tHTC tTCCD tSK(P-P) Parameter Differential Output Rise Time (20% to 80%) Differential Output Fall Time (80% to 20%) DP[n] Setup to STROBE DP[n] Hold to STROBE Transmitter Clock Input to Clock Output Delay CKSO Position Relative to DS Test Conditions See Figure 19 DIRI 1 1, 2.5 0 TBD TBD TBD TBD TBD TBD TBD TBD ps TBD Min Typ 0.6 0.6 Max 0.9 0.9 Units ns ns ns ns ns
See Figure (f 10 MHz) See Figure , DIRI CKREF STROBE See Figure , (Note ) CKREF Serialization Mode See Figure , (Note ) No CKREF Serialization Mode
Note 7: Skew is measured from either the rising or falling edge of the bit clock (CKSO) relative to the rising or falling edge of the data bit (DSO). CKSO and DSO have been designed to be edge aligned.
PLL Specifications
Symbol tJCC tTPLLS0 tTPLLD0 tTPLLD1 Parameter CKSO Clock Out Jitter (Cycle-to-Cycle) PLL Disable Time Loss of Clock PLL Power-Down Time (Note ) See Figure , (Note ) See Figure 3.0 Test Conditions Min Typ TBD 1000 10.0 20.0 Max Units ns Cycles us ns
Serializer Phase Lock Loop Stabilization Time See Figure
Note 8: This jitter specification is based on the assumption that PLL has a Ref Clock with cycle-to-cycle input jitter less than 2ns. Note 9: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Deserializer AC Electrical Characteristics
Symbol tS_DS tH_DS tRCOP tRCOL tRCOH tPDV tROLH tROHL Parameter Serial Port Setup Time DS to CKSI Serial Port Hold Time DS to CKSI CKP OUT Low Time CKP OUT High Time Data Valid to CKP HIGH Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Test Conditions See Figure , (Note ) See Figure , (Note ) See Figure 23 (Rising Edge Strobe) Serializer Source STROBE CKREF Where a (1/f)/14 (Note ) See Figure 23 (Rising Edge Strobe) Where a (1/f)/14 (Note ) CL 8pF See Figure Min 500 Typ Max Units ps ps T 200 7a3 7a3 7a 3.5 3.5 7a3 7.0 7.0 ns ns ns ns ns ns
500
17.8 7a3 7a3 7a3
Deserializer Clock Output (CKP OUT) Period See Figure 23
Note 10: Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew from the serializer, load variations and ISI and jitter effects. Note 11: Rising edge of CKP will appear approximately 7-bit times after the falling edge of the CKP output. Data will appear coincident with this falling edge. Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to STROBE for the serializer the CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain in 7 bit times.
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Preliminary FIN12AC Control Logic Timing Controls
Symbol tPHL_DIR, tPLH_DIR tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH Parameter Propagation Delay DIRI-to-DIRO Propagation Delay DIRI-to-DP Propagation Delay DIRI-to-DP Deserializer Disable Time: S0 or S1 to DP Deserializer Enable Time: S0 or S1 to DP Serializer Disable Time: S0 or S1 to CKSO, DS Serializer Enable Time: S0 or S1 to CKSO, DS Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW DIRI Figure DIRI Figure DIRI Figure DIRI Figure 1, S1(2) and S2(1) LOW-to-HIGH 1, S1(2) and S2(1) High-to-LOW 0, S1(2) 0 and S2(1) LOW-to-HIGH 0, S1(2) 0 and S2(1) LOW-to-HIGH Min TBD Typ TBD Max 10.0 7.0 10.0 7.0 10.0 7.0 10.0 Units ns ns ns ns ns ns ns
Capacitance
Symbol CIN CIO Parameter Capacitance of Input Only Signals, CKREF, STROBE, S1, S2, DIRI Capacitance of Parallel Port Pins DP[1:12] CIO-DIFF DIRI VDD DIRI VDD "1", S1 2.5V "1", S1 2.5V "0", PwnDwn 0, VDD 2.5V 0; 0, Test Conditions 0, Min Typ TBD TBD Max Units pF pF
Capacitance of Differential I/O Signals DIRI S1
TBD
pF
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Preliminary FIN12AC AC Loading and Waveforms
Note A: For All input pulses, tR or tF 1 ns
FIGURE 12. Differential CTL Output DC Test Circuit
FIGURE 13. Differential Receiver Voltage Definitions
FIGURE 14. "Worst Case" Serializer Test Pattern
FIGURE 15. CTL Output Load and Transition Times
FIGURE 16. LVCMOS Output Load and Transition Times
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Preliminary FIN12AC AC Loading and Waveforms
(Continued)
Setup: Mode0
"0" or "1"m MODE1
"1", SER/DES
"1"
FIGURE 17. Serial Setup and Hold Time
FIGURE 18. LVCMOS Clock Parameters
Setup: DIRI
"0", CKSI and DS are Valid Signals
Note: CKREF Signal is free running.
FIGURE 19. Deserializer Data Valid Window Time and Clock Output Parameters
FIGURE 20. Serializer PLL Lock Time
Note: STROBE
CKREF
FIGURE 21. Serializer Clock Propagation Delay
FIGURE 22. Deserializer Clock Propagation Delay
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Preliminary FIN12AC AC Loading and Waveforms
(Continued)
FIGURE 23. Differential Input Setup and Hold Times
FIGURE 24. Differential Output Signal Skew
Note: CKREF Signal can be stopped either HIGH or LOW
FIGURE 25. PLL Loss of Clock Disable Time
FIGURE 26. PLL Power-Down Time
Note: CKREF must be active and PLL must be stable
Note: If S1(2) transitioning then S2(1) must
0 for test to be valid.
FIGURE 27. Serializer Enable and Disable Time
FIGURE 28. Deserializer Enable and Disable Times
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Preliminary FIN12AC Tape and Reel Specification
TAPE FORMAT for USS-BGA
Dimensions are in millimeters Package 3.5 x 4.5 A0 B0 D D1 min 1.5 E F K0 P1 TYP 8.0 P0 TYP 4.0 P2 T TYP 0.3 TC W WC TYP 9.3
r0.10
TBD
r0.10
TBD
r0.05
1.55
r0.1
1.75
r0.1
5.5
r0.1
1.1
r0/05
2.0
r0.005
0.07
r0.3
12.0
Note: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
Dimensions are in millimeters Tape Width 8 12 16 Dia A max 330 330 330 Dim B min 1.5 1.5 1.5 Dia C Dia D min 20.2 20.2 20.2 Dim N min 178 178 178 Dim W1 Dim W2 max 14.4 18.4 22.4 Dim W3 (LSL - USL) 7.9 a 10.4 11.9 a 15.4 15.9 a 19.4
0.5/0.2
13.0 13.0 13.0
2.0/0
8.4 12.4 16.4
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Preliminary FIN12AC
TAPE FORMAT for MLP Package Designator MLX Tape Section Leader (Start End) Carrier Trailer (Hub End) MLP Embossed Tape Dimension Number Cavities 125 (typ) 2500/3000 75 (typ) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed
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Preliminary FIN12AC Physical Dimensions inches (millimeters) unless otherwise noted
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Package Number BGA042A
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Preliminary FIN12AC PSerDes Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square Package Number MLP032A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 21 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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